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I'm Subbu and I author the articles here on systemverilog.io. Thank you for signing up for the SVIO newsletter which is read by 1400+ engineers.

This site is dedicated to all aspects of hardware development. The content is divided into three sections

• Design - Core concepts in Computer Architecture, System Design and SoC/ASIC/FPGA Design.
• Verification - Formal Verification and Functional verification with SystemVerilog/UVM
• Engineering - The dynamics behind engineering culture, career development and lessons I've learned from my work experience.

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Here are a few popular articles you could explore on each topic.

Design

All Design Articles

• DDR4 Tutorial
• DDR4 Timing Parameters
• DDR4 Initialization, Training & Calibration

Verification

All Verification Articles

• SystemVerilog Assertions Tutorial
• Introduction to Formal Verification
• SystemVerilog Generate

Engineering

All Engineering Articles

• How to conduct a technical interview

I hope you enjoy what you read here and find it useful. Once again, thank you for subscribing. If you have any requests, questions or comments please write to me at subbu[AT]systemverilog.io.

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