When issuing consecutive ACTIVATE commands to banks of different bank groups, the ACTIVATE commands have to be separated by tRRD_S (row-to-row delay--short)
tRRD_L
If the banks belong to the same bank group, their ACTIVATEs have to be separated by tRRD_L (row-to-row delay--long)
tFAW
Four Activate Window or sometimes also called Fifth Activate Window is a timing restriction. tFAW specifies a window within which only four activate commands can be issued. So, you can issue ACTIVATE commands back-to-back with tRRD_S between them, but once you have completed 4 activates you cannot issue another one until the tFAW window expires.
Bank accesses to different banks' groups require less time delay between accesses than bank accesses to within the same bank's group. Bank accesses to different bank groups require tCCD_S (or short) delay between commands while bank accesses within the same bank group require tCCD_L (or long) delay between commands.
AL (Additive Latency)
With AL, the device allows a WRITE command to be issued immediately after the ACTIVATE command. The command is held for the time of AL before it is issued inside the device. This feature is supported to sustain higher bandwidths/speeds in the device.
CAS is the Column-Address-Strobe, i.e., when the column address is presented on the lines. CL is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. It is defined in the MR0 mode register. SDRAM data sheets typically specific what the CL needs to be set for a particular frequency of operation. See Fig 7
AL (Additive Latency)
With AL, the device allows a READ command to be issued immediately after the ACTIVATE command. The command is held for the time of AL before it is issued inside the device. This feature is supported to sustain higher bandwidths/speeds in the device.
RL (Read Latency)
This is the overall read latency and is defined as RL = CL + AL
tDQSCK (MIN/MAX)
describes the allowed range for a rising data strobe edge relative to the clock CK_t, CK_c
tDQSCK
is the actual position of a rising strobe edge relative to CK_t, CK_c
tQSH
describes the data strobe high pulse width
tQSL
tQSL - describes the data strobe low pulse width.
tDQSQ
This describes the latest valid transition of the associated DQ data pins. From the picture below you'll see that it is the time between when DQS transitions to the left edge of the DQ data-eye
tQH
Is the earliest invalid transition of the associated DQ pins. From the picture below you'll see that it is the time from when DQS goes high to the right egdge of the DQ data-eye.
CWL is the delay, in clock cycles, between the internal WRITE command and the availability of the first bit of input data. It is defined in Mode Register MR2.
WL (Write Latency)
This is the overall write latency and is defined as WL = CWL + AL
tDQSS (MIN/MAX)
describes the allowed range for a rising data strobe edge relative to CK
tDQSS
is the actual position of a rising strobe edge relative to CK
tDQSH
describes the data strobe high pulse width
tDQSL
describes the data strobe low pulse width
tWPST
This of this as "post-write". It is the time from when the last valid data strobe to when the strobe goes to HIGH, non-drive level.
tWPRE
This of this as "pre-write". It is the time between when the data strobe goes from non-valid (HIGH) to valid (LOW, initial drive level).
MRS command cycle time. It is the time required to complete the WRITE operation to the mode register and is the minimum time required between the two MRS commands shown in the tMRD Timing figure.
tMOD
is the minimum time required from an MRS command to a non MRS command, excluding DES.
